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# The CASPER Toolflow
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## What is mlib_devel?
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`mlib_devel` is a set of FPGA DSP libraries and programming tools maintained by the [Collaboration for Astronomical Signal Processing and Electronics Research (CASPER)](>). Within the collaboration, it is affectionately referred to as *The Toolflow.*

``mlib_devel`` allows you to generate signal processing designs using MATLAB's graphical programming tool `Simulink`. These designs can be turned into FPGA bitstreams and loaded onto a variety of supported hardware platforms to perform real-time digital signal processing systems. CASPER also provides a Python software library for interacting with running designs: [casperfpga ](

## Using mlib_devel

For more information about installing and using the CASPER Toolflow, see the project's [documentation](

CASPER also maintain a set of [tutorials](, designed to introduce new users to the toolflow.

> ***Updating an Existing Toolflow Installation***
>You can always update your installation of `mlib_devel` by pulling updated code from this repository. If you do this, chances are you'll need to update your Simulink models to match your new `mlib_devel` libraries. A script is provided to automate this process. With your model open and active, in your MATLAB prompt, run
> This script will resynchronize every CASPER block in your design with its latest library version. Depending on the size of your model, it may take many minutes to complete!
>As always, back up your designs before attempting such a major operation. And, if you experience problems, please riase Github issues!

## Directory structure

  <dd>Simulink DSP libraries</dd>
  <dd>Simulink libraries for tool-flow supported modules (ADC interfaces, Ethernet cores, etc.)</dd>
  <dd>HDL code and Xilinx EDK wrappers used in older (ROACH2 and earlier) versions of the toolflow.</dd>
  <dd><a href="">Sphinx documentation</a> for the software in this project.</dd>
    Python and MATLAB scripts required to drive the compilation process. Also platform-dependent configuration information and source-code for IP modules used by the toolflow in the following directories:
    <dd>YAML files defining the compile parameters and physical constraints of CASPER-supported FPGA platforms.</dd>
    <dd>Golden boot images for FPGA platforms which require them.</dd>
    <dd>HDL source files for all toolflow-suppled modules (eg. ADC interfaces, Ethernet cores, etc.).</dd>
    <dd>Codebase for embedded software processors used by the toolflow.</dd>
    <dd>Python classes for each yellow block in the simulink `xps_library`.</dd>