1. 19 Jul, 2019 4 commits
  2. 18 Jul, 2019 26 commits
  3. 17 Jul, 2019 10 commits
    • hpw1's avatar
      Fixed clock critical warnings for synthesis (Red Pitaya) · acf580b7
      hpw1 authored
      I now refer to the clock source pins instead of the clock name and this allows Vivado to identify the clocks during synthesis. Hence, there are no critical warnings.
    • hpw1's avatar
      Merge branch 'ordered-axi-map' into merge-staging-2019 · ec21d222
      hpw1 authored
      This contains the AXI memory mapping fix that sorts out the issue with
      multiple snapshots and brams, plus naming conventions.
    • Jack's avatar
      More AXI generation fixes · 12dc6b86
      Jack authored
      Had an issue where, if there were (eg) three 4-byte registers
      on the sw_reg device bus, the xml2vhdl code would generate
      a device with `byte_size="8"`.
      Traced this to an (I think) erroneous calculation of size in
      the xml2vhdl package.
      This commit also tweaks the verilog.py source so that sw_reg
      is not always placed last, but is placed in accordance with its size.
      This fixes my misunderstanding -- the top-level devices need to be
      N-byte aligned, not the underlying (32-bit) registers. Therefore
      we can't assume that the sw_reg block should go last. It may be
      relatively large.
      Also round up memory spaces to 2**n bytes before ordering. This
      shouldn't change anything, but means the calculation done by the toolflow
      and xml2vhdl should match.
    • hpw1's avatar
    • hpw1's avatar
      Removed reinterpret and cast in ADC yellow block · b20d48d8
      hpw1 authored
      The reinterpret and cast in the ADC yellow block has been removed. This has been tested and still works.
    • Jack's avatar
      Round up sw_reg memory space to a power of 2 bytes · 9605718e
      Jack authored
      This should mean it is automatically aligned appropriately
    • Jack's avatar
      Order axi memory devices largest to smallest · 0afa5a51
      Jack authored
      To try and comply with an xml2vhdl requirement that an
      N-byte device be aligned on an N-byte boundary.
      If all devices are 2^m bytes, this should work.
      It's unclear to me whether the alignment needs to be
      at the axi device level, or the sub-register level.
      If the former, then I don't think this will fix having (eg)
      random numbers of registers, since the total size of the sw_reg
      space will not be a power of 2 bytes (even though each register
      within the space is 2^2 = 4 bytes in size)
    • Jack's avatar
      Merge branch 'merge-staging-2019' of... · f8879cc8
      Jack authored
      Merge branch 'merge-staging-2019' of https://github.com/casper-astro/mlib_devel into merge-staging-2019
    • Jack Hickish's avatar
      Merge pull request #98 from casper-astro/post-merge-1gbe-fixes · 54260e4c
      Jack Hickish authored
      Post merge 1gbe fixes
    • Jack's avatar
      Change all prints to logging messages · 23f8fc77
      Jack authored
      Don't print top.v to screen.
      Remove some debugging parameter prints from verilog.py