1. 15 Dec, 2020 2 commits
  2. 22 Nov, 2020 1 commit
  3. 10 Nov, 2020 1 commit
  4. 19 Oct, 2020 2 commits
  5. 16 Oct, 2020 6 commits
  6. 15 Oct, 2020 1 commit
  7. 14 Oct, 2020 1 commit
  8. 13 Oct, 2020 1 commit
  9. 12 Oct, 2020 4 commits
  10. 09 Oct, 2020 2 commits
    • AdamI75's avatar
      Merge pull request #38 from ska-sa/wes_40gbe_extract · 46ed40c9
      AdamI75 authored
      QSFP 40GbE Constraint Fix
      46ed40c9
    • AdamI75's avatar
      QSFP 40GbE Constraint Fix · 27748875
      AdamI75 authored
      The 40GbE constraints fix that ensures the 40GbE PHY remains in the pblock was overwritten. I have added this back as it will prevent the compilation from failing when placing global clocks on region X0Y7 (only 12 out of 13 clock allowed in the X0Y7 region). This fix allows consecutive compilation of the 32K F-engine 64A model and to compile successfully each time.
      27748875
  11. 08 Oct, 2020 1 commit
  12. 28 Sep, 2020 1 commit
  13. 21 Sep, 2020 2 commits
  14. 16 Sep, 2020 1 commit
  15. 15 Sep, 2020 3 commits
  16. 10 Sep, 2020 1 commit
  17. 24 Aug, 2020 1 commit
  18. 03 Aug, 2020 1 commit
    • AdamI75's avatar
      Fixed F/W version path issue · cd9cdba4
      AdamI75 authored
      The folder structure has been changed. The skarab_parameters.vhd file, which contains the SKARAB firmware version is overwritten depending on whether the yaml file selects multiboot, golden or the toolflow image. This file was not being overwritten as the python script was still pointing to the "infrastructure" folder and not the new "skarab_inf" folder, which is located in the "hdl_sources" folder. This has been tested on skarab020522.
      cd9cdba4
  19. 31 Jul, 2020 2 commits
    • AdamI75's avatar
      Fixed DRC and methodology critical warnings · a1538173
      AdamI75 authored
      I have removed all critical warnings from the design rule check and methodology checks. I have also removed a few warnings. The current QoR score is 5 for a design with 3 x HMCs, 1 x 40GbE and 1 x 1GbE. There was an issue with the 1GbE clock constraints, which has been fixed. This has been tested on skarab020522.
      a1538173
    • wnew's avatar
      Adding the design and scripts to test the skarab onegbe · 239c6c10
      wnew authored
      Just adding these to the repo so that the 1gbe cores can be tested at ta later
      stage. This is a manual process but will set you off in the right direction.
      239c6c10
  20. 30 Jul, 2020 1 commit
  21. 29 Jul, 2020 3 commits
  22. 28 Jul, 2020 1 commit
    • AdamI75's avatar
      Removed ICAP Hold Netlist Violations · ded283f5
      AdamI75 authored
      The ICAP was clocked off a gated clock. I have removed the gated clock and increased the ICAP clock to 9.7MHz, which may speed up the FPGA configuration. The clock was set to 2.4MHz. This has removed the synthesis hold time violations. This has been tested on skarab020522 and skarab020202.
      ded283f5
  23. 27 Jul, 2020 1 commit