1. 16 Jul, 2020 4 commits
  2. 13 Jul, 2020 2 commits
    • Morag's avatar
      Documentation update: · 9702525e
      Morag authored
      Reworked layout for read-the-docs
      Updated installation guide
    • Morag's avatar
      Documentation update: · c2cdfa19
      Morag authored
      Reworked layout for read-the-docs
      Updated installation guide
  3. 15 Jun, 2020 1 commit
  4. 12 Jun, 2020 1 commit
  5. 11 Jun, 2020 2 commits
  6. 03 Jun, 2020 1 commit
  7. 01 Jun, 2020 2 commits
  8. 27 May, 2020 1 commit
    • tyronevb's avatar
      Fix issues encountered when trying to install casperfpga · 6dc00481
      tyronevb authored
      The setup.py file was defining progska as a Python module and a Python
      extension. As a result of this, katversion, a Python package that
      handles version information, was expecting an __init__.py file for
      progska. The setup.py file has been modified to treat progska only as a
      Python extension and not a module.
      Resolves: ST-227
  9. 14 May, 2020 2 commits
  10. 12 May, 2020 1 commit
    • tyronevb's avatar
      Refactor gbe classes to not store device network state · 929a31b2
      tyronevb authored
      The ip address, port and mac address of the processing nodes were
      previously stored locally in class attributes. This change sees these
      attributes call methods that retrieve this information from the
      processing node. All other methods that rely on these attributes behave
      as expected without modification.
      This commit applies this change to the parent gbe class and the
      fortygbe child class.
      Resolves: CBFTASKS-821 (jira)
  11. 04 May, 2020 1 commit
  12. 30 Apr, 2020 2 commits
    • tyronevb's avatar
      Add error handling for out-of-range wishbone transactions · 4babdd8a
      tyronevb authored
      Adds error handing for out-of-range wishbone transactions (rw/wr) for
      the SKARAB transport platform.
      Addressing out-of-range wishbone memory addresses previously caused the
      SKARAB board to lockup. A new MicroBlaze version catches these errors
      and propagates them back up to casperfpga where the user is informed
      that the transaction failed due to an out-of-range address.
      Maintains backward compatibility with older MicroBlaze versions.
      Resolves: ST-153
    • tyronevb's avatar
      Refactor various wishbone r/w methods to support error handling · f801a222
      tyronevb authored
      Not all top-level reads/writes were calling the defined low-level
      wishbone read/write methods. This has been corrected and enables more
      robust error handling.
  13. 29 Apr, 2020 1 commit
    • tyronevb's avatar
      Handle out-of-memory range errors for wishbone r/w · 32471319
      tyronevb authored
      Add error handling for reads and writes to wishbone addresses that are
      out of range. Initial support for error handling added. Modified
      wishbone command packet structures to include field for error_status.
      Maintains backwards compatibility with older MicroBlaze versions. Needs
      to be tested. And other methods of transport_skarab need to be
      refactored to take full advantage of this.
  14. 22 Apr, 2020 1 commit
  15. 17 Apr, 2020 1 commit
    • tyronevb's avatar
      Fix get_gbe_core_details method for fortygbe core · 20c90934
      tyronevb authored
      The method reading the registers wasn't correctly parsing the bitfields
      in the various registers. This has been fixed.
      Also removed any hard coded addresses and uses the defined register map
  16. 01 Apr, 2020 1 commit
    • tyronevb's avatar
      Add backwards compatibility for older fpg headers · 8bd4e4fe
      tyronevb authored
      Older fpg headers don't contain the address and size of the 40GbE cores.
      This causes an error with the new changes to support multiple 40GbE
      links. This hot fix allows older fpg files to still work - it hard codes
      the address and size of the 40GbE core.
  17. 30 Mar, 2020 1 commit
  18. 27 Mar, 2020 2 commits
  19. 26 Mar, 2020 1 commit
  20. 24 Mar, 2020 1 commit
  21. 19 Mar, 2020 2 commits
    • tyronevb's avatar
      Add support for multiple 40GbE links · 597b0167
      tyronevb authored
      Individual 40GbE cores are now instantiated independently. Information
      e.g. addresses, parameters are read from the fpg file header. No
      parameters are hardcoded in casperfpga.
      Also removed support for legacy register maps for the GbE cores.
    • tyronevb's avatar
      Add support for 40GbE Multilinks · f41b1b7c
      tyronevb authored
      Work in progress. Added support for additional cores and dynamically
      assigning the address based on the contents of the fpg file header.
      Still requires testing and clean up.
  22. 18 Mar, 2020 2 commits
    • Tyrone van Balla's avatar
      Merge pull request #94 from ska-sa/upload_to_ram_and_prog_fix · d6819370
      Tyrone van Balla authored
      Clean up upload_to_ram_and_program method - JIRA: CBFTASKS-803
    • tyronevb's avatar
      Clean up upload_to_ram_and_program method · dbfe8eb6
      tyronevb authored
      Cleaned up the upload_to_ram_and_program method. If programming a board
      fails, we no longer populate the system information. Also cleaned up the
      passing of unique parameters to the transport layers. e.g. the
      chunk_size parameter for skarab. This can be passed as a kwarg to
      upload_to_ram_and_program and is handled appropriately in the underlying
      transport layer.
  23. 26 Feb, 2020 3 commits
  24. 25 Feb, 2020 3 commits
  25. 24 Feb, 2020 1 commit