There is no need to add the xml2vhdl path to the startsg.local anymore. The xml2vhdl has been made a submodule and the path has been added to the
startsg file. I have also implemented a fix for running "jasper" from the command line. It does need to be tested and may not work.

The new uBlaze does the following: Added a bounce-link command to the command line interface.  "un-deprecated" dhcp unbound-state monitoring. Fix: unaligned wishbone memory access from casperfpga. Logging - changed the default log-level from 'debug' to 'info'.

The SKARAB and Red Pitaya slx models now reflect the latest yellow blocks.

Tested with ADC and DAC tutorial.

This commit works with the SKARAB intro tutorial and HMC tutorial. The MMCMs are no longer cascaded, but driven from the same source clock. The HMC design gets the cdc_synchroniser source from the utils
folder now.

Tutorial fixes

Removed duplicate info.

Merge branch 'merge-staging-2019' of https://github.com/casper-astro/mlib_devel into merge-staging-2019

The "<<<<< HEAD" text was causing the compile to fail. This has been removed.

Add docstring laying out the basic rules of platform YellowBlock addi…

Merge branch 'merge-staging-2019' of https://github.com/casper-astro/mlib_devel into merge-staging-2019

This reverts commit bfa83479a9a7ae3f17485bf5970956ca0602876f.

 Conflicts:
	xps_library/@xps_forty_gbe/xps_forty_gbe.m
           - Modified in error. This file is redundant with JASPER. Deleted
	xps_library/xps_library.slx
           - Regenerated the xps library with BB's script

Fix software register links in sync_gen block
Replace spect_power block from soak-test library

One of the ten_gbe subclasses hadn't been updated with the
new ten_gbe class name

It appears to be broken for n_taps>2.
The pfb_fir_generic block support asynchronous mode if that is required.

The adder_tree was updated to change the latency parameter to csp_latency,
But these PFB blocks were not updated to use this new parameter, and would
error with "adder_tree has no parameter 'latency'".

Address issue #13 -- add casper_get_version script

Running casper_get_ver in the MATLAB prompt will print various version
info for the OS, MATLAB, Xilinx tools, repo version.

Hopefully will be useful in bug reporting.

Adds code from Arash

I think it is silly.

- Overwrite xps_library.slx on save even if it shows as being changed on disk since opening.
- Note the previous reversion of ca7afada because this has been fixed by an alternative
  method in a previous ska-sa commit.

This reverts commit ff992a90.

 Conflicts:
	xps_library/xps_library.slx
        - Kept ours. Need to regenerate library

 Conflicts:
	jasper_library/test_models/test_onegbe.slx
        - took ours. Assume these test files are disposable
	jasper_library/test_models/test_tgbe.slx
        - took ours. Assume these test files are disposable
	jasper_library/yellow_blocks/yellow_block_typecodes.py
        - the mx175 branch (via the SNAP2 devs) use separate TYPECODE values
          for different ethernet cores. With the new memory map, all ethernet
          cores share a common interface, so this is redundant.
          This commit removes references to these typecodes (1GBE_ETH, 10GBE_ETH)
          here and in associated yellow blocks / microblaze code.
          All ethernet cores for all platforms now use the TYPECODE_ETH code (1).
	xps_library/xps_library.slx
        - took ours. Need to regenenerate library.

 Conflicts:
	casper_library/casper_library_misc.slx
        - Merged this with the simulink merge tool :-S!
        - SKA-SA changes were to update to Simulink 2018
          (changes of name of "latency" variable, etc.)
        - casper-astro changes were to fix sw_regs in sync gen
        - check vs commits
          - 536fed07
          - d3d63bb0
          - f343a393
          - c030fa71
          - 20966491
          - 78e9bcf3
	jasper_library/memory.py
        - took ska-sa. Docstring changes only
	xps_library/xps_library.slx
        - took casper-astro. Need to regenerate manually.

Dual support for the 10-bit and 14-bit Red Pitaya development boards.

- Renamed the red_pitaya.yaml file to red_pitaya_10.yaml.
- Added .yaml file for 14-bit Red Pitaya platform.
- Modified Red Pitaya ADC and DAC masks to allow for 10-bit or 14-bit selection.
- Modified Red Pitaya platform YellowBlock for 10-bit or 14-bit selection.
- Modified Red Pitaya ADC and DAC YellowBlocks for 10-bit or 14-bit selection.