1. 13 Jul, 2019 9 commits
  2. 12 Jul, 2019 3 commits
  3. 09 Jul, 2019 1 commit
  4. 28 Jun, 2019 1 commit
    • wnew's avatar
      Red Pitaya BRAM fix · 238dabc5
      wnew authored
      This fixes the broken bram address generation in cofeinfo and the xml2vhdl
      output
      238dabc5
  5. 27 Jun, 2019 2 commits
    • wnew's avatar
      Red pitaya bram support · 98ad439e
      wnew authored
      1. Added support for the BRAMs in the RP flow
      2. Fixed up the clocking and reset architecture.
      
      BRAMs not working 100% yet as there is some issue with the AXI2VHDL
      generation that wont allow me to put the correct address space or
      maybe it expects it in bytes not words, I just dont care anymore!
      And I want to go home. Why oh why, Adamm did you have to volunteer
      us for the hardware porting workshop?
      98ad439e
    • Amish's avatar
      Merge pull request #85 from AdamI75/master · f489c346
      Amish authored
      Added How To for Matlab R2018a and Vivado 2018.2
      f489c346
  6. 26 Jun, 2019 1 commit
  7. 24 Jun, 2019 4 commits
  8. 21 Jun, 2019 2 commits
    • AdamI75's avatar
      Fixed Hardcoded name · a0231f76
      AdamI75 authored
      There was a hardcoded design name in the python script, which meant that if the slx file name changes then certain software registers going to the processor would not be connected properly. This has been fixed and tested.
      a0231f76
    • AdamI75's avatar
      Removed ADC LA code and fixed MMCM bug · 0e65cf79
      AdamI75 authored
      I have commented out the ADC debug code and the there was a DIVCLK generic on the ADC and DAC MMCM, which was linked to the usr_clk MMCM. This has been hard coded to 1 now. I have tested the usr_clk at 125MHz and 200MHz. The ADC and DAC functionality work with both clock frequencies.
      0e65cf79
  9. 20 Jun, 2019 3 commits
    • AdamI75's avatar
      Fixed ADC and DAC channel 2 · f8577704
      AdamI75 authored
      I fixed the bit ranges in the DAC and ADC firmware. I was selecting the incorrect bits for channel 2. This has been fixed. I can now use Channel 1 ADC with channel 1 DAC and Channel 2 ADC with channel 2 DAC. This has been tested on the Red Pitaya - using an external logic analyser, signal generator and oscilloscope.
      f8577704
    • AdamI75's avatar
      Added ADC and DAC debugging Fixes · 221cf22e
      AdamI75 authored
      The Channel 1 ADC and DAC is fully operational and has been tested on the Red Pitaya. I am still debugging channel 2. There is some debug functionality in this code, which will be removed once channel 2 is working. I have also added more timing constraints. The design meets the timing.
      221cf22e
    • gcallanan's avatar
      dfd54182
  10. 19 Jun, 2019 1 commit
    • AdamI75's avatar
      Fixed Infrastructure bugs and added constraints · 002db093
      AdamI75 authored
      The MMCM multiply settings did not fit so changed the multiplication factor to 8 from 12 and the output divide factor to 4 from 6. The adc reset signal was also always asserted, so I fixed that - had a different name to the PLL locked signal. I also fixed some incorrect ADC firmware ranges for the counter. I have added in the constraints for the ADC, DAC and clock. The DAC is set to false path for now, as that is what Stemlab have done for the Red Pitaya project constraints. The project compiles and still needs to be fully tested.
      002db093
  11. 18 Jun, 2019 2 commits
    • AdamI75's avatar
      Fixed up ADC and DAC verilog and python · 440e8587
      AdamI75 authored
      The ADC yellow block now compiles through, but I need to test still. I made changes to the red_pitaya.v infrastructure port constraints and fixed up verilog firmware issues. I connected all the resets correctly.
      440e8587
    • wnew's avatar
      updating the rp test design and fix to libraries · 13617954
      wnew authored
      The red pitaya test design is now the same as tutorial 1
      Fixed a bug which still tried to use the work library for vhdl files
      13617954
  12. 17 Jun, 2019 6 commits
    • wnew's avatar
      Updates and fixes to red pitaya · c132e501
      wnew authored
      1. fixed hard coded path
      2. added reset from the zync
      3. added the resets into the infrastructure
      c132e501
    • AdamI75's avatar
      Added DAC to xps_library · d5b1181e
      AdamI75 authored
      I added the red pitaya DAC to the xps_library.slx. This is untested.
      d5b1181e
    • AdamI75's avatar
      Added initial DAC yellow block · f63a1601
      AdamI75 authored
      I have added the initial DAC yellow block, which includes python script and firmware. This has not been tested yet.
      f63a1601
    • wnew's avatar
      Geting the registers working on the Red Pitaya · 0f15d42d
      wnew authored
      1. The AXI4Lite registers now work on the red pitaya
      2. The clocking infrastructure now provides clocks for the ADC and DAC.
      The clocks still need to be constrained and the resets need to be implemented
      0f15d42d
    • wnew's avatar
      Red pitaya clocking changes · e9584a49
      wnew authored
      e9584a49
    • AdamI75's avatar
      Simplified ADC yellow block · b710768d
      AdamI75 authored
      The ADC yellow block is untested, but has been simplified - removed decimation and modes for now. The underlying firmware driver has been implemented, but not tested.
      b710768d
  13. 14 Jun, 2019 5 commits