- 13 Jul, 2019 9 commits
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Jack Hickish authored
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Jack Hickish authored
I think it is silly.
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Jack Hickish authored
- Overwrite xps_library.slx on save even if it shows as being changed on disk since opening. - Note the previous reversion of ca7afada because this has been fixed by an alternative method in a previous ska-sa commit.
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Jack Hickish authored
This reverts commit ff992a90.
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Jack Hickish authored
Conflicts: xps_library/xps_library.slx - Kept ours. Need to regenerate library
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Jack Hickish authored
Conflicts: jasper_library/test_models/test_onegbe.slx - took ours. Assume these test files are disposable jasper_library/test_models/test_tgbe.slx - took ours. Assume these test files are disposable jasper_library/yellow_blocks/yellow_block_typecodes.py - the mx175 branch (via the SNAP2 devs) use separate TYPECODE values for different ethernet cores. With the new memory map, all ethernet cores share a common interface, so this is redundant. This commit removes references to these typecodes (1GBE_ETH, 10GBE_ETH) here and in associated yellow blocks / microblaze code. All ethernet cores for all platforms now use the TYPECODE_ETH code (1). xps_library/xps_library.slx - took ours. Need to regenenerate library.
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Jack Hickish authored
Conflicts: casper_library/casper_library_misc.slx - Merged this with the simulink merge tool :-S! - SKA-SA changes were to update to Simulink 2018 (changes of name of "latency" variable, etc.) - casper-astro changes were to fix sw_regs in sync gen - check vs commits - 536fed07 - d3d63bb0 - f343a393 - c030fa71 - 20966491 - 78e9bcf3 jasper_library/memory.py - took ska-sa. Docstring changes only xps_library/xps_library.slx - took casper-astro. Need to regenerate manually.
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Jack Hickish authored
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Jack Hickish authored
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- 12 Jul, 2019 3 commits
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Jack Hickish authored
Dual support for the 10-bit and 14-bit Red Pitaya development boards.
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talonmyburgh authored
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talonmyburgh authored
- Renamed the red_pitaya.yaml file to red_pitaya_10.yaml. - Added .yaml file for 14-bit Red Pitaya platform. - Modified Red Pitaya ADC and DAC masks to allow for 10-bit or 14-bit selection. - Modified Red Pitaya platform YellowBlock for 10-bit or 14-bit selection. - Modified Red Pitaya ADC and DAC YellowBlocks for 10-bit or 14-bit selection.
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- 09 Jul, 2019 1 commit
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Your Name authored
For some reason this breaks machines with out ipython version 5. Go figure.
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- 28 Jun, 2019 1 commit
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wnew authored
This fixes the broken bram address generation in cofeinfo and the xml2vhdl output
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- 27 Jun, 2019 2 commits
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wnew authored
1. Added support for the BRAMs in the RP flow 2. Fixed up the clocking and reset architecture. BRAMs not working 100% yet as there is some issue with the AXI2VHDL generation that wont allow me to put the correct address space or maybe it expects it in bytes not words, I just dont care anymore! And I want to go home. Why oh why, Adamm did you have to volunteer us for the hardware porting workshop?
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Amish authored
Added How To for Matlab R2018a and Vivado 2018.2
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- 26 Jun, 2019 1 commit
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AdamI75 authored
I have added a how to procedure for Matlab R2018a and Vivado 2018.2 to cover the gaps in the install procedures.
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- 24 Jun, 2019 4 commits
- 21 Jun, 2019 2 commits
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AdamI75 authored
There was a hardcoded design name in the python script, which meant that if the slx file name changes then certain software registers going to the processor would not be connected properly. This has been fixed and tested.
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AdamI75 authored
I have commented out the ADC debug code and the there was a DIVCLK generic on the ADC and DAC MMCM, which was linked to the usr_clk MMCM. This has been hard coded to 1 now. I have tested the usr_clk at 125MHz and 200MHz. The ADC and DAC functionality work with both clock frequencies.
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- 20 Jun, 2019 3 commits
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AdamI75 authored
I fixed the bit ranges in the DAC and ADC firmware. I was selecting the incorrect bits for channel 2. This has been fixed. I can now use Channel 1 ADC with channel 1 DAC and Channel 2 ADC with channel 2 DAC. This has been tested on the Red Pitaya - using an external logic analyser, signal generator and oscilloscope.
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AdamI75 authored
The Channel 1 ADC and DAC is fully operational and has been tested on the Red Pitaya. I am still debugging channel 2. There is some debug functionality in this code, which will be removed once channel 2 is working. I have also added more timing constraints. The design meets the timing.
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gcallanan authored
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- 19 Jun, 2019 1 commit
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AdamI75 authored
The MMCM multiply settings did not fit so changed the multiplication factor to 8 from 12 and the output divide factor to 4 from 6. The adc reset signal was also always asserted, so I fixed that - had a different name to the PLL locked signal. I also fixed some incorrect ADC firmware ranges for the counter. I have added in the constraints for the ADC, DAC and clock. The DAC is set to false path for now, as that is what Stemlab have done for the Red Pitaya project constraints. The project compiles and still needs to be fully tested.
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- 18 Jun, 2019 2 commits
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AdamI75 authored
The ADC yellow block now compiles through, but I need to test still. I made changes to the red_pitaya.v infrastructure port constraints and fixed up verilog firmware issues. I connected all the resets correctly.
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wnew authored
The red pitaya test design is now the same as tutorial 1 Fixed a bug which still tried to use the work library for vhdl files
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- 17 Jun, 2019 6 commits
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wnew authored
1. fixed hard coded path 2. added reset from the zync 3. added the resets into the infrastructure
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AdamI75 authored
I added the red pitaya DAC to the xps_library.slx. This is untested.
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AdamI75 authored
I have added the initial DAC yellow block, which includes python script and firmware. This has not been tested yet.
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wnew authored
1. The AXI4Lite registers now work on the red pitaya 2. The clocking infrastructure now provides clocks for the ADC and DAC. The clocks still need to be constrained and the resets need to be implemented
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wnew authored
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AdamI75 authored
The ADC yellow block is untested, but has been simplified - removed decimation and modes for now. The underlying firmware driver has been implemented, but not tested.
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- 14 Jun, 2019 5 commits
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wnew authored
This will allow us to select a clock frequency for the user to run the DSP at.
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wnew authored
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wnew authored
Committing these so others can build. Not yet working but almost there!
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AdamI75 authored
This is untested. I converted the mode select from strings to integers for generics
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AdamI75 authored
This is untested, but it contains the yellow block, mask scripts, python and yaml platform updates.
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