This might one day make for a cleaner message if something goes wrong and
this script isn't being called directly (i.e. isn't sys.argv[0])

This prevents other instances of argparse elsewhere (in xml2vhdl)
from trying to process these flags

I now refer to the clock source pins instead of the clock name and this allows Vivado to identify the clocks during synthesis. Hence, there are no critical warnings.

This contains the AXI memory mapping fix that sorts out the issue with
multiple snapshots and brams, plus naming conventions.

Had an issue where, if there were (eg) three 4-byte registers
on the sw_reg device bus, the xml2vhdl code would generate
a device with `byte_size="8"`.
Traced this to an (I think) erroneous calculation of size in
the xml2vhdl package.

This commit also tweaks the verilog.py source so that sw_reg
is not always placed last, but is placed in accordance with its size.
This fixes my misunderstanding -- the top-level devices need to be
N-byte aligned, not the underlying (32-bit) registers. Therefore
we can't assume that the sw_reg block should go last. It may be
relatively large.

Also round up memory spaces to 2**n bytes before ordering. This
shouldn't change anything, but means the calculation done by the toolflow
and xml2vhdl should match.

The reinterpret and cast in the ADC yellow block has been removed. This has been tested and still works.

This should mean it is automatically aligned appropriately

To try and comply with an xml2vhdl requirement that an
N-byte device be aligned on an N-byte boundary.
If all devices are 2^m bytes, this should work.

It's unclear to me whether the alignment needs to be
at the axi device level, or the sub-register level.
If the former, then I don't think this will fix having (eg)
random numbers of registers, since the total size of the sw_reg
space will not be a power of 2 bytes (even though each register
within the space is 2^2 = 4 bytes in size)

Merge branch 'merge-staging-2019' of https://github.com/casper-astro/mlib_devel into merge-staging-2019

Post merge 1gbe fixes

Don't print top.v to screen.
Remove some debugging parameter prints from verilog.py

Didn't check for functionality.

There is no need to add the xml2vhdl path to the startsg.local anymore. The xml2vhdl has been made a submodule and the path has been added to the
startsg file. I have also implemented a fix for running "jasper" from the command line. It does need to be tested and may not work.

The new uBlaze does the following: Added a bounce-link command to the command line interface.  "un-deprecated" dhcp unbound-state monitoring. Fix: unaligned wishbone memory access from casperfpga. Logging - changed the default log-level from 'debug' to 'info'.

The SKARAB and Red Pitaya slx models now reflect the latest yellow blocks.

Tested with ADC and DAC tutorial.

This commit works with the SKARAB intro tutorial and HMC tutorial. The MMCMs are no longer cascaded, but driven from the same source clock. The HMC design gets the cdc_synchroniser source from the utils
folder now.

Tutorial fixes

Removed duplicate info.

Merge branch 'merge-staging-2019' of https://github.com/casper-astro/mlib_devel into merge-staging-2019

The "<<<<< HEAD" text was causing the compile to fail. This has been removed.

Add docstring laying out the basic rules of platform YellowBlock addi…

Merge branch 'merge-staging-2019' of https://github.com/casper-astro/mlib_devel into merge-staging-2019

This reverts commit bfa83479a9a7ae3f17485bf5970956ca0602876f.

 Conflicts:
	xps_library/@xps_forty_gbe/xps_forty_gbe.m
           - Modified in error. This file is redundant with JASPER. Deleted
	xps_library/xps_library.slx
           - Regenerated the xps library with BB's script

Fix software register links in sync_gen block
Replace spect_power block from soak-test library

One of the ten_gbe subclasses hadn't been updated with the
new ten_gbe class name

It appears to be broken for n_taps>2.
The pfb_fir_generic block support asynchronous mode if that is required.