Updated real-time status port implementation for the different naming
conventions for DT parts. Also added synchronizers where necessary to safely
pass rts signals to the appropriate clock domain. Fixed an issue where sysref
gate is to only be added when mts is enabled.

More work needs to be done to properly capture and pass signals in to the user
design where the signal originates in a different clock domain.

Correct DAC port generation for dual-tile ADCs. This fixes a bug seen on
zcu208 when targeting all DAC locations.

Fix configuration issues in DDC/DUC between gen 2 and gen 3 hardware. This fixes
a bug where an invalid configuration value was forwaraded to Vivado for gen 2
hardware.

Fix word width, decimation, and interpolator options for DACs

could use some more work to

fixes bug that still prevents proper configuration of parts like the zcu111 that
have different number and types of tiles

fixes a bug that would incorrectly set the odd slice mixermode to I/Q mode when
toggling the even slice

properly support all platforms with new rfdc mask

We have been here before, see commit 165c2c9e...

The 100G registers were not accessible because the naming convention in the
yellow block did not match how the axi4lite made the nets and wired the design
up. However, adopting the need for a `design_name` in the 100G didn't make sense
as there is no real convenient way to do so.

How the axi4lite generates seems to be the larger issue and making sure that
both a yellow block adding registers as part of a mempry map and the axi4lite
follow the same convention is not really transparent. It is also too easy to not
be consistent. For example, because `sys_block` uses "sys" the ports need to be
added using this same name. Knowing this needs to be done is not obvious. Making
adding the ports that end up being used by the registers in the axi4lite
interconnect usually a "trial and error" experience. It would help if a single
entity were responsible for keeping track of adding the wires where they needed to
be... not exactly trivial as it would take some redesign of the axi work.

Fixes DAC arch properties, implementation inconsistencies, and other improvements

See merge request !2

Includes the fix to correctly update rfdc gateway's when copying yb from another
model file or renaming within the current one.

The mask now configures the `has clock` in the System Clocking Tab for the
selected platform.

Adds decimation and interpolation modes between different generations

Commits the updated rfdc yb mask and `xps_library` for additions that would have
been cumulative up to this point from the last three commits. Those changes in
yellow block update the interpolation and adc samples for adc/dac when

the dialogs woudl re-enable when needing to remain disabled. Also made logic
match recent changes to fix dac and be as close as possible

better supports this capability by automatically configuring neighboring odd
slices, disable as needed, and handle mixer parameter changes and enable/disable
of the tiles

This should fix more than it breaks...

Simplifies the mask logic for the dac in a few places. Continues reconciling
tile/slice architecture from previous commit with changes to
`get_rfsoc_properties` and utilize that information to simplify logic and begin
removing static hard-coded variables.

This also fixes a bug where the dac mixer mode could not be configured in coarse
operation. It allowed for it to be selected but always defaulted back to fine

There are still issues configuring outputs in I/Q mode. The change in logic has
broken some of that capability. There are also still some bugs with enable
option for odd slices not being selectable when it should be. This typically
requires toggling the even slice neighbor a few ways to get the odd slice back.

there was an error in how dacs implemented the tile architecture confusing it
with the number of tiles on a board

Doc updates

documentation updates: made stylistic choice to replace MATLAB with Matlab so the docs are less screamy, reworked Running the Toolflow to be neater and clearer

Rfsocs/devel m2021a spectrometer

Latency parameters were taken from `realtimeradio/mlib_devel@5a63ff3` an one was
missed and was to be be added to a relational block correctly align fft operation

Changed data type rule to output of gain block ot also be 32-bit

The simulink gain block is for left shifts. This is needed for example when
spliting a 32-bit swreg into multiple bitfields. The default rule for the gain
block with fixed point data types is for full precision and so the output type
is at least twice the input type. This seems to cause errors with this version
of  sysgen/model composer as now the gateways are enforcing checks that input
bitwidths are compatible.

Rfsocs/devel m2021a spectrometer

compiling with these blocks prior to this change would result unspressed output
to the command prompt such as `f_type = 'fixed'`, `f_type = 'custom'`,
`enfixpt = 'on'`, and others.

This was because mask initializations in the `cmult`, `butterfly`, `biplex`,
`fft_unscrambler` for data type mask parameters executed and variables used to
switch configuration based on type was unsuprssed (not ending in `;`).

`pfb_fir_real` was missing its mask initialization call. This would prevent the
block from responding to parameter configuration.

`pfb_fir` was missing the `c_to_ri` block in the `first_tap`. The `pfb_fir`
would build out but fail to compile with errors of unconnected multiply blocks.

the barrel switcher does not have a latency parameter member this causes the
complex fft to error in building out

Update Configuring-the-Toolflow.md

Update the documentation for the addition of the `COMPOSER_PATH` env var