We have been here before, see commit 165c2c9e...
The 100G registers were not accessible because the naming convention in the
yellow block did not match how the axi4lite made the nets and wired the design
up. However, adopting the need for a design_name in the 100G didn't make sense
as there is no real convenient way to do so.
How the axi4lite generates seems to be the larger issue and making sure that
both a yellow block adding registers as part of a mempry map and the axi4lite
follow the same convention is not really transparent. It is also too easy to not
be consistent. For example, because sys_block uses "sys" the ports need to be
added using this same name. Knowing this needs to be done is not obvious. Making
adding the ports that end up being used by the registers in the axi4lite
interconnect usually a "trial and error" experience. It would help if a single
entity were responsible for keeping track of adding the wires where they needed to
be... not exactly trivial as it would take some redesign of the axi work.