Synchrnous vs. Asynchronous reads
The output of the SRLShiftReg and Phasecomp modules are Asynchronous reads. This may result in poor timing results when working with place and route and we may need to add pipeline registers to improve timing.
Synchronous reads register the output of a read from a memory effectively adding an additional latency. Asynchronous reads must go through the memory and out to the next logic element. Adding (most likely) to the net delay. Adding synchronous reads would require them to be updated everywhere (SRLShiftRegister modules and phase comp modules).
Without back pressure being implemented in the design (e.g., AXIS tready) the pipeline registers should be straight forward. But the way the System Verilog test bench interfaces with output products of the python simulation model would no longer be compatible because the Python simulator also assumes asynchronous reads. It may not be easy to edit the python code to add the latencies but, it could be possible to change the control in the System Verilog for when to check the right answers.