Synthesis Inference Boundary
Currently the delay buffers shift-register logic (SRL) is implemented using LUTs as a Xilinx SRL32 using configurable blocks (CBs - the basic Xilinx FPGA building block). In order to prevent fanout of reset/enable signals on the shift registers a single "head" register receives the reset signal that loads the reset value that propagates through the data path. This is implemented in the DelayBuf
module using SRLShiftReg
modules. Each PE
has 3 of these DelayBuf
s. The sumbuf
contains the partial multiply accumulate operations (MACs).
Efficient DSP usage will immediately register the output of a MAC to have the best clk-q time for faster circuits. The question is will the synthesis tool be smart enough to know that the output of the MAC is actually registered in this head register, or because they live in two different modules the synthesis tools is hindered from inferring such behavior?