This branch restructured the verilog.py class in order to create more
effective comments and structuring of auto-generated Verilog code.
It also removed un-neccessary comments in yellow block classes since
they will now be generated on the fly. It also fixed some naming
dependencies of xps_library blocks after new xps_library rework.

Reverting to commit a4e34cb0: "Fix README mistakes." after inappropiately adding the build directory. Only want to include build html files.

This reverts commit a4e34cb0.

Removed old html files. Will now include _build directory in repo because these are the local html files we would like for Simulink Block Help.

CASPER Block Documentation. Created from using the crawl_block_docs.py script to crawl old wiki pages. Pandoc was used to convert html to rst for autogenerated Sphinx documentation.

Sorted signals, ports, parameters, assignments, and instances using ascending order. Added top.pickle object. Working on sorted and printing ports by input, output, and inouts.

Generated correct top.v code for tut_intro and tut_ten_gbe after restructing Verilog.py code to generate better comments. Removed comments from all yellow_block scripts to prevent double printing of the same comment in top.v. Fixed matlab draw script dependencies of now remapped xps_library blocks.

Restructed VerilogModule objects to all be dictionaries, which results in nested dictionaries. Added Parameter class. And cur_blk attribute, which can be used to show who declared what in top.v. Tested and working with intro_tutorial, however bug in ten_gbe_tutorial.

Reworking xps_library for each block to have its own model for proper block version control. Removing deprecated blocks/code. Added gpio_bidir yellow block to library.

Update Golden Image

Added support for VLAN networking

Add build version to microblaze executable

Update xps_library/adc_snap_init.m

Fix a bug in toolflow.py

Hera devel

This has MB with 100ms timeout

Update gbe_rx.v