Forgot to checkout commit object that I was reverting to.

.gitignore

@@ -31,6 +31,5 @@ xps_base/XPS_ROACH2_base/system.xmp.updated
 *.local
 vivado_pid*.str
 
-.Xil/
+# ignore docs build directory
 docs/_build/
-!docs/_build/html/src

docs/README.md

 # Sphinx style documentation
 
-##Building:
+## Building:
 - Install requirements using `pip install -r requirements.txt`
 - Build using `make html` which will build the documentation in the `_build/` directory.
\ No newline at end of file

docs/index.rst

@@ -218,8 +218,6 @@ System Blocks
 
 :doc:`gpio <src/GPIO>`       (GPIO)
 
-:doc:`gpio_bidir <src/gpio_bidir>`      (Bi-directional GPIO)
-
 :doc:`qdr <src/Qdr>`     (QDR)
 
 :doc:`snapshot <src/Snapshot>`       (Snapshot Capture)
@@ -249,7 +247,6 @@ System Blocks
     src/Dac
     src/Dram
     src/GPIO
-    src/gpio_bidir
     src/Qdr
     src/Snapshot
     src/Snap

html/64ADCx64-12.html

+<!-- start content -->
+			<p><a href="images/b/b8/ADC64x12_block.pdf" class="internal" title="ADC64x12 block.pdf"> ADC64 Block Diagram</a>
+</p><p><a href="images/2/29/ADC64x12_PXS_testjig.pdf" class="internal" title="ADC64x12 PXS testjig.pdf">PXS Test Jig</a>
+</p><p><a href="images/7/70/ADC64x12_PXSADC_Top_Level.pdf" class="internal" title="ADC64x12 PXSADC Top Level.pdf">PXSADC Top Level</a>
+</p><p><a href="images/3/3a/ADC64x12_PXSADC_PL_20080110.xls" class="internal" title="ADC64x12 PXSADC PL 20080110.xls">PXS Spreadsheet</a>
+</p><p>The 64 input 12 bit ADC board was developed by Rick Raffanti.
+the board has been tested at 65 Msps using Rick's verilog interface,
+but the simulink yellow block has only been tested at 50 Msps so far.
+</p>
\ No newline at end of file

html/Adc.html

+<!-- start content -->
+			<p><b>Block:</b> ADC (<code>adc</code>)<br />
+<b>Block Author</b>: Pierre Yves Droz<br />
+<b>Document Author</b>: Ben Blackman<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a>
+<ul>
+<li class="toclevel-2 tocsection-5"><a href="#Usage"><span class="tocnumber">4.1</span> <span class="toctext">Usage</span></a></li>
+<li class="toclevel-2 tocsection-6"><a href="#Connecting_the_Hardware"><span class="tocnumber">4.2</span> <span class="toctext">Connecting the Hardware</span></a></li>
+<li class="toclevel-2 tocsection-7"><a href="#ADC_Background_Information"><span class="tocnumber">4.3</span> <span class="toctext">ADC Background Information</span></a></li>
+</ul>
+</li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>The ADC block converts analog inputs to digital outputs. Every clock cycle, the inputs are sampled and digitized to 8 bit binary point numbers in the range of [-1, 1) and are then output by the adc.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> ADC board
+</td><td> adc_brd
+</td><td> Select which ADC port to use on the IBOB.
+</td></tr>
+<tr>
+<td> ADC clock rate (MHz)
+</td><td> adc_clk_rate
+</td><td> Sets the clock rate of the ADC, must be at least 4x the IBOB clock rate.
+</td></tr>
+<tr>
+<td> ADC interleave mode
+</td><td> adc_interleave
+</td><td> Check for 1 input, uncheck for 2 inputs.
+</td></tr>
+<tr>
+<td> Sample period
+</td><td> sample_period
+</td><td> Sets the period at which the adc outputs samples (ie 2 means every other cycle).
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> sim_in
+</td><td> IN
+</td><td> double
+</td><td> The analog signal to be digitized if interleave mode is selected. Note: For simulation only.
+</td></tr>
+<tr>
+<td> sim_i
+</td><td> IN
+</td><td> double
+</td><td> The first analog signal to be digitized if interleave mode is unselected. Note: For simulation only.
+</td></tr>
+<tr>
+<td> sim_q
+</td><td> IN
+</td><td> double
+</td><td> The second analog signal to be digitized if interleave mode is unselected. Note: For simulation only.
+</td></tr>
+<tr>
+<td> sim_sync
+</td><td> IN
+</td><td> double
+</td><td> Takes a pulse to be observed at the output to measure the delay through the block. Note: For simulation only.
+</td></tr>
+<tr>
+<td> sim_data_valid
+</td><td> IN
+</td><td> double
+</td><td> A signal that is high when inputs are valid. Note: For simulation only.
+</td></tr>
+<tr>
+<td> oX
+</td><td> OUT
+</td><td> Fix_8_7
+</td><td> A signal that represents sample X+1 (Ex. o0 is the 1st sample, o7 is the 8th sample). Used if interleave mode is on.
+</td></tr>
+<tr>
+<td> iX
+</td><td> OUT
+</td><td> Fix_8_7
+</td><td> A signal that represents sample X+1 (Ex. i0 is the 1st sample, o3 is the 4th sample). Used if interleave mode is off.
+</td></tr>
+<tr>
+<td> qX
+</td><td> OUT
+</td><td> Fix_8_7
+</td><td> A signal that represents sample X+1 (Ex. q0 is the 1st sample, q3 is the 4th sample). Used if interleave mode is off.
+</td></tr>
+<tr>
+<td> outofrangeX
+</td><td> OUT
+</td><td> boolean
+</td><td> A signal that represents when samples are outside the valid range.
+</td></tr>
+<tr>
+<td> syncX
+</td><td> OUT
+</td><td> boolean
+</td><td> A signal that is high when the sync pulse offset by X if interleave mode is unselected, or 2X if interleave mode is selected is high (Ex. sync2 is the pulse offset by 2 if interleave is off or offset by 4 if interlave is on).
+</td></tr>
+<tr>
+<td> data_valid
+</td><td> OUT
+</td><td> boolean
+</td><td> A signal that is high when the outputs are valid.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<h3> <span class="mw-headline" id="Usage"> Usage </span></h3>
+<p>The ADC block can take 1 or 2 analog input streams. The first input should be connected to input i and the second to input q if it is being used. The inputs will then be digitized to <code>Fix_8_7</code> numbers between [-1, 1). For a single input, the <code>adc</code> samples its input 8 times per IBOB clock cycle and outputs the 8 samples in parallel with o0 being the first sample and o7 the last sample. For 2 inputs, the <code>adc</code> samples both inputs 4 times per IBOB clock cycle and then outputs them in parallel with i0-i3 corresponding to input i and q0-q3 corresponding to input q. In addition to having 2 possible inputs, each IBOB can interface with 2 <code>adc</code>s for a total of 4 inputs or 2 8-sample inputs per IBOB. 
+</p>
+<h3> <span class="mw-headline" id="Connecting_the_Hardware"> Connecting the Hardware </span></h3>
+<p>To hook up the ADC board, attach the clock SMA cable to the clk_i port, the first input to the I+ port, and the second input to the Q+ port. Check the hardware on the ADC board near the input pins. There should be for 4 square chips in a straight line. If there are only 3, the second input, Q+, may not work. Note that if you chose <code>adc0_clk</code>, make sure to plug the ADC board in to the adc0 port. The same applies if you chose <code>adc1_clk</code> to plug the board into adc1 port. If you are using both ADCs, then you need to plug a clock into both clk_i inputs and you should probably run them off of the same signal generator. 
+</p>
+<h3> <span class="mw-headline" id="ADC_Background_Information"> ADC Background Information </span></h3>
+<p>The ADC board was designed to mate directly to an IBOB board through ZDOK connectors for high-speed serial data I/O. Analog data is digitized using an Atmel AT84AD001B dual 8-bit ADC chip which can digitize two streams at 1 Gsample/sec or a single stream at 2 Gsample/sec. This board may be driven with either single-ended or differential inputs.
+</p>
\ No newline at end of file

html/Adc083000.html

+<!-- start content -->
+			<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Simulink_.28User.29_Outputs"><span class="tocnumber">1</span> <span class="toctext">Simulink (User) Outputs</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#DCM_Phase_Adjustment"><span class="tocnumber">2</span> <span class="toctext">DCM Phase Adjustment</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Pcore_Architecture"><span class="tocnumber">3</span> <span class="toctext">Pcore Architecture</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Future_Features_.28to_be_implemented.29"><span class="tocnumber">4</span> <span class="toctext">Future Features (to be implemented)</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Simulink_.28User.29_Outputs"> Simulink (User) Outputs </span></h2>
+<ul><li> 8 lanes of 8-bit data, of Simulink type Fix_8_7.
+</li><li> 4 "syncs" for each cycle of the clock signal output from the ADC board, each corresponding to a different cycle of the original undivided clock (which cycle is indicated by the signal index) original un-divided clock signal
+</li><li> 4 "out of range" signals to indicate either positive or negative value saturation (must examine data to determine which) in the same orientation as the sync signals
+</li><li> 1 data valid signal. Self explanatory name.
+</li></ul>
+<h2> <span class="mw-headline" id="DCM_Phase_Adjustment"> DCM Phase Adjustment </span></h2>
+<p>There have been reports of stability issues at higher ADC clock rates (&gt;350MHz). Adjusting the DCM phase seems to solve the problem.
+</p><p>The DCM phase can be manually tuned by changing two lines of Verilog.
+</p><p>In xps_lib, navigate to:
+</p>
+<pre>XPS_ROACH_base/pcores/adc083000x2_interface_v1_00_a/hdl/verilog
+</pre>
+<p>Open these three files:
+</p>
+<pre>adc083000_board_phy.v
+adc083000_board_phy_demux.v
+adc083000_demux_interface.v
+</pre>
+<p>Find these two lines in each file:
+</p>
+<pre>.CLKOUT_PHASE_SHIFT("NONE")
+.PHASE_SHIFT(0)
+</pre>
+<p>Change "NONE" to "FIXED", and set PHASE_SHIFT to 30.
+</p><p>The PHASE_SHIFT parameter can range from -255 to 255, but tests indicate that 30 is the optimal setting.
+</p>
+<h2> <span class="mw-headline" id="Pcore_Architecture"> Pcore Architecture </span></h2>
+<p>LVDS Data =&gt; IBUFDS =&gt; DDR Register =&gt; IORegister =&gt; IORegister =&gt; Asynchronous FIFO =&gt; Simulink
+</p><p>Hopefully a diagram will be soon to follow.
+</p>
+<h2> <span class="mw-headline" id="Future_Features_.28to_be_implemented.29"> Future Features (to be implemented) </span></h2>
+<ul><li> Serial interface
+<ul><li> The <a href="/wiki/ADC1x3000-8" title="ADC1x3000-8">main ADC chip</a> supports a serial interface to set phase/gains for the two sub-ADCs, which are interleaved together for the user to form
+</li></ul>
+</li></ul>

html/Adder_tree.html

+<!-- start content -->
+			<p><b>Block:</b> Adder Tree (<code>adder_tree</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Aaron Parsons<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Sums all inputs using a tree of adds and delays.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> No. of inputs.
+</td><td> n_inputs
+</td><td> The number of inputs to be summed.
+</td></tr>
+<tr>
+<td> Add Latency
+</td><td> latency
+</td><td> The latency of each stage through the adder tree.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> sync
+</td><td> in
+</td><td> Boolean
+</td><td> Indicates the next clock cycle containing valid data
+</td></tr>
+<tr>
+<td> din
+</td><td> in
+</td><td> Inherited
+</td><td> A number to be summed.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Sums all inputs using a tree of adds and delays. Total latency is <span class="texhtml"><i>c</i><i>e</i><i>i</i><i>l</i>(<i>l</i><i>o</i><i>g</i><sub>2</sub>(<i>n</i><sub><i>i</i></sub><i>n</i><i>p</i><i>u</i><i>t</i><i>s</i>)) * <i>l</i><i>a</i><i>t</i><i>e</i><i>n</i><i>c</i><i>y</i></span>.
+</p>
\ No newline at end of file

html/Barrel_switcher.html

+<!-- start content -->
+			<p><b>Block:</b> Barrel Switcher (<code>barrel_switcher</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Aaron Parsons<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Maps a number of inputs to a number of outputs by rotating In(N) to Out(N+M) (where M is specified on the sel input), wrapping around to Out1 when necessary.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Number of inputs
+</td><td> n_inputs
+</td><td> The number of parallel inputs (and outputs).
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> sync
+</td><td> in
+</td><td> Boolean
+</td><td> Indicates the next clock cycle contains valid data
+</td></tr>
+<tr>
+<td> In
+</td><td> in
+</td><td> Inherited
+</td><td> The stream(s) to be transposed.
+</td></tr>
+<tr>
+<td> sync_out
+</td><td> out
+</td><td> Boolean
+</td><td> Indicates that data out will be valid next clock cycle.
+</td></tr>
+<tr>
+<td> Out
+</td><td> out
+</td><td> Inherited
+</td><td> The transposed stream(s).
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Maps a number of inputs to a number of outputs by rotating In(N) to Out(N+M) (where M is specified on the sel input), wrapping around to Out1 when necessary.
+</p>
\ No newline at end of file

html/Bit_reverse.html

+<!-- start content -->
+			<p><b>Block:</b> Bit reverser (<code>bit_reverse</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Aaron Parsons<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Reverses the bit order of the input. Input must be unsigned with binary point at position 0. Costs nothing in hardware.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> No. of bits.
+</td><td> n_bits
+</td><td> Specifies the width of the input.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> in
+</td><td> in
+</td><td> UFix_x_0
+</td><td> The input signal.
+</td></tr>
+<tr>
+<td> out
+</td><td> out
+</td><td> UFix_x_0
+</td><td> The output.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Reverses the bit order of the input. Input must be unsigned with binary point at position 0. Costs nothing in hardware.
+</p>
\ No newline at end of file

html/C_to_ri.html

+<!-- start content -->
+			<p><b>Block:</b> Complex to Real-Imag Block (<code>c_to_ri</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Aaron Parsons<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Outputs real and imaginary components of a complex input. Useful for simplifying interconnects. See also <a href="/wiki/Ri_to_c" title="Ri to c">ri_to_c</a>.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Bit Width
+</td><td> n_bits
+</td><td> Specifies width of real/imag components. Assumed equal for both components.
+</td></tr>
+<tr>
+<td> Binary Point
+</td><td> bin_pt
+</td><td> Specifies the binary point location in the real/imaginary components. Assumed equal for both components.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> UFix_x_0
+</td><td> Complex input, real in MSB, imaginary in LSB.
+</td></tr>
+<tr>
+<td> r
+</td><td> out
+</td><td> Fix_x_y
+</td><td> Real signed output, binary point specified by parameter.
+</td></tr>
+<tr>
+<td> i
+</td><td> out
+</td><td> Fix_x_y
+</td><td> Imaginary signed output, binary point specified by parameter.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Outputs real and imaginary components of a complex input. Useful for simplifying interconnects. See also <a href="/wiki/Ri_to_c" title="Ri to c">ri_to_c</a>.
+</p>
\ No newline at end of file

html/Cmult_4bit_br*.html

+<!-- start content -->
+			<p><b>Block:</b> Conjugating Complex 4-bit Multiplier Implemented in Block RAM (<code>cmult_4bit_br*</code>)<br />
+<b>Block Author</b>:&nbsp;?<br />
+<b>Document Author</b>:&nbsp;?<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Perform a conjugating complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> + <i>b</i><i>d</i>) + (<i>b</i><i>c</i> &minus; <i>a</i><i>d</i>)<i>i</i></span>. Implements the logic in Block RAM.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Multiplier Latency
+</td><td> mult_latency
+</td><td> The latency through a multiplier.
+</td></tr>
+<tr>
+<td> Add Latency
+</td><td> add_latency
+</td><td> The latency through an adder.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 1.
+</td></tr>
+<tr>
+<td> b
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 1.
+</td></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 2.
+</td></tr>
+<tr>
+<td> d
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 2.
+</td></tr>
+<tr>
+<td> real
+</td><td> out
+</td><td> Inherited
+</td><td> ac+bd
+</td></tr>
+<tr>
+<td> imag
+</td><td> out
+</td><td> Inherited
+</td><td> -ad+bc
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Perform a conjugating complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> + <i>b</i><i>d</i>) + (<i>b</i><i>c</i> &minus; <i>a</i><i>d</i>)<i>i</i></span>. Implements the logic in Block RAM. Each 4 bit real multiplier is implemented as a lookup table with 4b+4b=8b of address.
+</p>
\ No newline at end of file

html/Cmult_4bit_br.html

+<!-- start content -->
+			<p><b>Block:</b> Complex 4-bit Multiplier Implemented in Block RAM (<code>cmult_4bit_br</code>)<br />
+<b>Block Author</b>: Block Author<br />
+<b>Document Author</b>: Document Author<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Perform a complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> &minus; <i>b</i><i>d</i>) + (<i>a</i><i>d</i> + <i>b</i><i>c</i>)<i>i</i></span>. Implements the logic in Block RAM.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Multiplier Latency
+</td><td> mult_latency
+</td><td> The latency through a multiplier.
+</td></tr>
+<tr>
+<td> Add Latency
+</td><td> add_latency
+</td><td> The latency through an adder.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 1.
+</td></tr>
+<tr>
+<td> b
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 1.
+</td></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 2.
+</td></tr>
+<tr>
+<td> d
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 2.
+</td></tr>
+<tr>
+<td> real
+</td><td> out
+</td><td> Inherited
+</td><td> ac-bd
+</td></tr>
+<tr>
+<td> imag
+</td><td> out
+</td><td> Inherited
+</td><td> ad-bc
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Each 4 bit real multiplier is implemented as a lookup table with 4b+4b=8b of address.
+</p>
\ No newline at end of file

html/Cmult_4bit_em*.html

+<!-- start content -->
+			<p><b>Block:</b> Conjugating Complex 4-bit Multiplier Implemented in Dedicated Multipliers. (<code>cmult_4bit_em*</code>)<br />
+<b>Block Author</b>:&nbsp;?<br />
+<b>Document Author</b>: Vinayak Nagpal<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Perform a conjugating complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> + <i>b</i><i>d</i>) + (<i>b</i><i>c</i> &minus; <i>a</i><i>d</i>)<i>i</i></span>. Implements the logic in dedicated multipliers.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Multiplier Latency
+</td><td> mult_latency
+</td><td> The latency through a multiplier.
+</td></tr>
+<tr>
+<td> dd Latency
+</td><td> add_latency
+</td><td> The latency through an adder.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 1.
+</td></tr>
+<tr>
+<td> b
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 1.
+</td></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 2.
+</td></tr>
+<tr>
+<td> d
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 2.
+</td></tr>
+<tr>
+<td> real
+</td><td> out
+</td><td> Inherited
+</td><td> ac+bd
+</td></tr>
+<tr>
+<td> imag
+</td><td> out
+</td><td> Inherited
+</td><td> -ad+bc
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Perform a conjugating complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> + <i>b</i><i>d</i>) + (<i>b</i><i>c</i> &minus; <i>a</i><i>d</i>)<i>i</i></span>. Implements the logic in dedicated multipliers. Each 4 bit real multiplier is implemented as a lookup table with 4b+4b=8b of address.
+</p>
\ No newline at end of file

html/Cmult_4bit_em.html

+<!-- start content -->
+			<p><b>Block:</b> Complex 4-bit Multiplier Implemented in Embedded Multipliers (<code>cmult_4bit_em</code>)<br />
+<b>Block Author</b>:&nbsp;?<br />
+<b>Document Author</b>:&nbsp;?<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Perform a complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> &minus; <i>b</i><i>d</i>) + (<i>a</i><i>d</i> + <i>b</i><i>c</i>)<i>i</i></span>. Implements the logic in embedded multipliers.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Multiplier Latency
+</td><td> mult_latency
+</td><td> The latency through a multiplier.
+</td></tr>
+<tr>
+<td> dd Latency
+</td><td> add_latency
+</td><td> The latency through an adder.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 1.
+</td></tr>
+<tr>
+<td> b
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 1.
+</td></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 2.
+</td></tr>
+<tr>
+<td> d
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 2.
+</td></tr>
+<tr>
+<td> real
+</td><td> out
+</td><td> Inherited
+</td><td> ac-bd
+</td></tr>
+<tr>
+<td> imag
+</td><td> out
+</td><td> Inherited
+</td><td> ad+bc
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Perform a complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> &minus; <i>b</i><i>d</i>) + (<i>a</i><i>d</i> + <i>b</i><i>c</i>)<i>i</i></span>. Implements the logic in embedded multipliers. Each 4 bit real multiplier is implemented as a lookup table with 4b+4b=8b of address.
+</p>
\ No newline at end of file

html/Cmult_4bit_sl*.html

+<!-- start content -->
+			<p><b>Block:</b> Conjugating Complex 4-bit Multiplier Implemented in Slices (<code>cmult_4bit_sl*</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Vinayak Nagpal<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Perform a conjugating complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> + <i>b</i><i>d</i>) + (<i>b</i><i>c</i> &minus; <i>a</i><i>d</i>)<i>i</i></span>. Implements the logic in Slices.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Multiplier Latency
+</td><td> mult_latency
+</td><td> The latency through a multiplier.
+</td></tr>
+<tr>
+<td> Add Latency
+</td><td> add_latency
+</td><td> The latency through an adder.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 1.
+</td></tr>
+<tr>
+<td> b
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 1.
+</td></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 2.
+</td></tr>
+<tr>
+<td> d
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 2.
+</td></tr>
+<tr>
+<td> real
+</td><td> out
+</td><td> Inherited
+</td><td> ac+bd
+</td></tr>
+<tr>
+<td> imag
+</td><td> out
+</td><td> Inherited
+</td><td> -ad+bc
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Perform a conjugating complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> + <i>b</i><i>d</i>) + (<i>b</i><i>c</i> &minus; <i>a</i><i>d</i>)<i>i</i></span>. Implements the logic in Slices.
+</p>
\ No newline at end of file

html/Cmult_4bit_sl.html

+<!-- start content -->
+			<p><b>Block:</b> Complex 4-bit Multiplier Implemented in Slices (<code>cmult_4bit_sl</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Vinayak Nagpal<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Perform a complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> &minus; <i>b</i><i>d</i>) + (<i>a</i><i>d</i> + <i>b</i><i>c</i>)<i>i</i></span>. Implements the logic in Slices.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Multiplier Latency
+</td><td> mult_latency
+</td><td> The latency through a multiplier.
+</td></tr>
+<tr>
+<td> Add Latency
+</td><td> add_latency
+</td><td> The latency through an adder.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 1.
+</td></tr>
+<tr>
+<td> b
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 1.
+</td></tr>
+<tr>
+<td> c
+</td><td> in
+</td><td> Inherited
+</td><td> The real component of input 2.
+</td></tr>
+<tr>
+<td> d
+</td><td> in
+</td><td> Inherited
+</td><td> The imaginary component of input 2.
+</td></tr>
+<tr>
+<td> real
+</td><td> out
+</td><td> Inherited
+</td><td> ac-bd
+</td></tr>
+<tr>
+<td> imag
+</td><td> out
+</td><td> Inherited
+</td><td> ad+bc
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Perform a complex multiplication <span class="texhtml">(<i>a</i> + <i>b</i><i>i</i>)(<i>c</i> &minus; <i>d</i><i>i</i>) = (<i>a</i><i>c</i> &minus; <i>b</i><i>d</i>) + (<i>a</i><i>d</i> + <i>b</i><i>c</i>)<i>i</i></span>. Implements the logic in Slices.
+</p>
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html/Complex_addsub.html

+<!-- start content -->
+			<p><b>Block:</b> Complex Adder/Subtractor (<code>complex_addsub</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Ben Blackman<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a>
+<ul>
+<li class="toclevel-2 tocsection-5"><a href="#Usage"><span class="tocnumber">4.1</span> <span class="toctext">Usage</span></a></li>
+</ul>
+</li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>This block does a complex addition and subtraction of 2 complex numbers, <code>a</code> and <code>b</code>, and spits out 2 complex numbers, <code>a+b</code> and <code>a-b</code>.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Bit Width
+</td><td> BitWidth
+</td><td> The number of bits in its input.
+</td></tr>
+<tr>
+<td> Add Latency
+</td><td> add_latency
+</td><td> The latency of the adders/subtractors.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> a
+</td><td> IN
+</td><td> 2*BitWidth Fixed point
+</td><td> The first complex number whose higher BitWidth bits are its real part and lower BitWidth bits are its imaginary part.
+</td></tr>
+<tr>
+<td> b
+</td><td> IN
+</td><td> 2*BitWidth Fixed point
+</td><td> The second complex number whose higher BitWidth bits are its real part and lower BitWidth bits are its imaginary part.
+</td></tr>
+<tr>
+<td> a+b
+</td><td> OUT
+</td><td> 2*BitWidth Fixed point
+</td><td> Upper BitWidth bits are real(<code>a</code>)+real(<code>b</code>). Lower BitWidth bits are imaginary(<code>a</code>)-imaginary(<code>b</code>).
+</td></tr>
+<tr>
+<td> a-b
+</td><td> OUT
+</td><td> 2*BitWidth Fixed point
+</td><td> Upper BitWidth bits are imaginary(<code>a</code>)+imaginary(<code>b</code>). Lower BitWidth bits are real(<code>b</code>)-real(<code>a</code>).
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<h3> <span class="mw-headline" id="Usage"> Usage </span></h3>
+<p>The top output, <code>a+b</code>, is a complex output whose real part equals the sum of the real parts of <code>a</code> and <code>b</code>. The imaginary part of <code>a+b</code> equals the difference of the imaginary parts of <code>a</code> and <code>b</code>. The bottom output, <code>a-b</code>, is a complex output whose real part equals the sum of the imaginary parts of <code>a</code> and <code>b</code>.The imaginary part of <code>a-b</code> equals the difference of the real parts of <code>b</code> and <code>a</code>. The latency of this block is 2*<code>add_latency</code>.
+</p>
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html/Correlation_Control_Block.html

+<!-- start content -->
+			<p><b>Block:</b> Correlation Control Block (<code>CCB</code>)<br />
+<b>Block Author</b>: Kaushal D. Buch, GMRT, India<br />
+<b>Document Author</b>: Kaushal D. Buch, GMRT, India<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Ports"><span class="tocnumber">2</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Description"><span class="tocnumber">3</span> <span class="toctext">Description</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Test_Results"><span class="tocnumber">4</span> <span class="toctext">Test Results</span></a></li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Correlation control block takes a pair of uncorrelated digital noise sources in the input and generates a pair of output noise with correlation. The amount of correlation can be selected from a set of pre-defined values. This block is an extension to the Gaussian Random Number Generator block in the CASPER library (<a href="https://casper.berkeley.edu/wiki/Gaussian_Random_Number_Gen" class="external free" rel="nofollow">https://casper.berkeley.edu/wiki/Gaussian_Random_Number_Gen</a>)
+</p>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> noise_in1 to noise_in4
+</td><td> IN
+</td><td> 8-bit signed
+</td><td> Four uncorrelated streams from the output of the Gaussian Random Number Generator.
+</td></tr>
+<tr>
+<td> noise_in5 to noise_in8
+</td><td> IN
+</td><td> 8-bit signed
+</td><td> Four uncorrelated streams from the output of the Gaussian Random Number Generator.
+</td></tr>
+<tr>
+<td> corr_sel_in
+</td><td> IN
+</td><td> 3-bit unsigned
+</td><td> Selection of the amount of correlation coefficient at the output.
+<pre>Selection -
+0 - uncorrelated (~0%)
+1 - 5% correlation
+2 - 10% correlation
+3 - 20% correlation
+4 - 50% correlation
+5 - 100% correlation
+</pre>
+</td></tr>
+<tr>
+<td> corr_noise_out1 to corr_noise_out4
+</td><td> OUT
+</td><td> 8-bit signed (Fix8_7)
+</td><td> Four streams of output digital noise.
+</td></tr>
+<tr>
+<td> corr_noise_out5 to corr_noise_out8
+</td><td> OUT
+</td><td> 8-bit signed (Fix8_7)
+</td><td> Four streams of output digital noise.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<p>Correlation Control Block(CCB) is an extension to the existing library block called Gaussian Random Number Generator (GRNG). CCB can be used along with GRNG block to get variable correlation between two input noise channels.
+</p><p>The correlation control block uses an uncorrelated noise source whose coupling to the two input channels is varied to control the correlation. By varying the ratio of the variance of common noise source (Pc) to the variance of input channels (P1 and P2) we get the correlation coefficient as Pc / (P+Pc) (Note: We assume that P1 = P2 = P, i.e. components from input channels have same variance).
+</p><p>Currently, there is a facility to select the following values of correlation through software register - 0% (uncorrelated), 5%, 10%, 20%, 50% and 100% (correlated).
+</p>
+<h2> <span class="mw-headline" id="Test_Results"> Test Results </span></h2>
+<p>The variable correlation digital noise source design was tested with the GRNG for a 300MHz BW PoCo with 0.89s integration on ROACH.
+</p>
\ No newline at end of file

html/Dac.html

+<!-- start content -->
+			<p><b>Block:</b> DAC (<code>dac</code>)<br />
+<b>Block Author</b>: Henry Chen<br />
+<b>Document Author</b>: Ben Blackman<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a>
+<ul>
+<li class="toclevel-2 tocsection-5"><a href="#Usage"><span class="tocnumber">4.1</span> <span class="toctext">Usage</span></a></li>
+</ul>
+</li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>The DAC block converts 4 digital inputs to 1 analog output. The <code>dac</code> runs at 4x FPGA clock frequency, outputting analog converted samples 0 through 3 each FPGA clock cycle.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> DAC board
+</td><td> dac_brd
+</td><td> Select which IBOB port to run this <code>dac</code>.
+</td></tr>
+<tr>
+<td> DAC clock rate (MHz)
+</td><td> dac_clk_rate
+</td><td> The clock rate to run the <code>dac</code>. Must be 4x FPGA clock rate.
+</td></tr>
+<tr>
+<td> Sample period
+</td><td> sample_period
+</td><td> Sets the period at which the <code>dac</code> outputs samples (ie 2 means every other cycle).
+</td></tr>
+<tr>
+<td> Show Implementation Parameters
+</td><td> show_param
+</td><td> Allows the user to set the implementation parameters.
+</td></tr>
+<tr>
+<td> Invert output clock phase
+</td><td> invert_clock
+</td><td> When unchecked, the <code>dac</code> samples the data aligned with the clock. When checked, the <code>dac</code> samples the data aligned with an inverted clock.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> dataX
+</td><td> IN
+</td><td> Fix_9_8
+</td><td> One of 4 digital inputs to be converted to analog.
+</td></tr>
+<tr>
+<td> sim_out
+</td><td> OUT
+</td><td> double
+</td><td> Analog output of <code>dac</code>. Note: For simulation only.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<h3> <span class="mw-headline" id="Usage"> Usage </span></h3>
+<p>The <code>dac</code> takes 4 <code>Fix_9_8</code> inputs and outputs an analog stream. The <code>dac</code> runs at 4x the FPGA clock speed.
+</p><p>To be updated.
+</p>
\ No newline at end of file

html/Dds.html

+<!-- start content -->
+			<p><b>Block:</b> DDS (<code>dds</code>)<br />
+<b>Block Author</b>: Aaron Parsons<br />
+<b>Document Author</b>: Ben Blackman<br />
+</p>
+<table id="toc" class="toc"><tr><td><div id="toctitle"><h2>Contents</h2></div>
+<ul>
+<li class="toclevel-1 tocsection-1"><a href="#Summary"><span class="tocnumber">1</span> <span class="toctext">Summary</span></a></li>
+<li class="toclevel-1 tocsection-2"><a href="#Mask_Parameters"><span class="tocnumber">2</span> <span class="toctext">Mask Parameters</span></a></li>
+<li class="toclevel-1 tocsection-3"><a href="#Ports"><span class="tocnumber">3</span> <span class="toctext">Ports</span></a></li>
+<li class="toclevel-1 tocsection-4"><a href="#Description"><span class="tocnumber">4</span> <span class="toctext">Description</span></a>
+<ul>
+<li class="toclevel-2 tocsection-5"><a href="#Usage"><span class="tocnumber">4.1</span> <span class="toctext">Usage</span></a></li>
+</ul>
+</li>
+</ul>
+</td></tr></table><script>if (window.showTocToggle) { var tocShowText = "show"; var tocHideText = "hide"; showTocToggle(); } </script>
+<h2> <span class="mw-headline" id="Summary"> Summary </span></h2>
+<p>Generates sines and cosines of different phases and outputs them in parallel.
+</p>
+<h2> <span class="mw-headline" id="Mask_Parameters"> Mask Parameters </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Parameter
+</th><th> Variable
+</th><th> Description
+</th></tr>
+<tr>
+<td> Frequency Divisions (M)
+</td><td> freq_div
+</td><td> Denominator of the frequency.
+</td></tr>
+<tr>
+<td> Frequency (? /M<span class="texhtml"> * $2$ * </span>pi)
+</td><td> freq
+</td><td> Numerator of the frequency.
+</td></tr>
+<tr>
+<td> Parallel LOs
+</td><td> num_lo
+</td><td> Number of parallel local oscillators.
+</td></tr>
+<tr>
+<td> Bit Width
+</td><td> n_bits
+</td><td> Bit width of the outputs.
+</td></tr>
+<tr>
+<td> Latency
+</td><td> latency
+</td><td> Description
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Ports"> Ports </span></h2>
+<table width="500" border="1" cellpadding="3">
+<tr>
+<th> Port
+</th><th> Dir
+</th><th> Data Type
+</th><th> Description
+</th></tr>
+<tr>
+<td> sinX
+</td><td> OUT
+</td><td> Fix_(n_bits)_(n_bits-1)
+</td><td> Sine output corresponding to the Xth local oscillator.
+</td></tr>
+<tr>
+<td> cosX
+</td><td> OUT
+</td><td> Fix_(n_bits)_(n_bits-1)
+</td><td> Cosine output corresponding to the Xth local oscillator.
+</td></tr>
+</table>
+<h2> <span class="mw-headline" id="Description"> Description </span></h2>
+<h3> <span class="mw-headline" id="Usage"> Usage </span></h3>
+<p>There are <code>sin</code> and <code>cos</code> outputs each equal to the minimum of <code>num_lo</code> and <code>freq_div</code>. If <code>num_lo</code> <span class="texhtml"> &gt;  = </span> <code>freq_div</code>/<code>freq</code>, then the outputs will be <code>lo_const</code>s. Otherwise each output will oscillate depending on the values of <code>freq_div</code> and <code>freq</code>. If the outputs oscillate, then there will be a latency of <code>latency</code> and otherwise there will be zero latency.
+</p>
\ No newline at end of file