mask bug

rfsoc fixes

- recover startup of vitis from startsg

- temporary fix to remove jasper `XILINX_PATH` from env before launching xsct
for device tree generation. Later versions of the tool rely on `XILINX_PATH`
that is setup by xilinx and we clobber it on startup

- temporary fix to bump rfdc version

M2021a

M2021a

This fixes port/wire names in the sys_block yellow block and the reg_name used
in its axi4lite_interface so that everything matches up and gets properly
connected in top.v.

Fixed VHDL update for Vivado 2021.1

I initialise the array to zero using new VHDL standard

HMC IP Fix

Removing those weird assign statements

These are not required any more as the signals are connected up
directly.
It probably should have been done this way in the first place.

The hmc_user_axi_fifo.xci ip was locked. I upgraded it to get it to compile.

M2021a

40gbe changes so skarab 40gbe (hopefully) works alongside other 40gbe…

40gbe changes so skarab 40gbe (hopefully) works alongside other 40gbes. Tested on a skarab and works

Updating the gpio driving the au50 cattrip pin

This should have been driving the pin low and not high.

Still need to investigate why the SARAO au50s work with this set to 1.

Au50