... | ... | @@ -144,8 +144,9 @@ Figure 6: Fine spectrum plot of the ALPACA OSPFB output with a single tone input |
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</div>
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### 6.1.2 Packetizer
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The document linked below specifies the detailed ethernet jumbo packet format for
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data transfer from the RFSoC F-engine digitizer and frequency channelizer, to
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The Packetizer organizes sampled and frequency-channelized data into
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ethernet jumbo packet format for
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ransfer from the RFSoC F-engine digitizer and frequency channelizer, to
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the GPU XB-engine digital beamformer. The data transfer is handled by a 60-port
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100 GbE ethernet switch, which performs a large "corner turn" operation to
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reorder data from being sequenced by antenna index to sequencing by frequency
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... | ... | @@ -154,26 +155,6 @@ channels. After the corner turn, these jumbo packets are re-routed so that each |
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GPU process 25 (out of 1300) frequency channels for all 138 (+6 spares) antenna
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signal streams.
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Another important aspect of the packetizer format design shown in the linked
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document below is the way frequency channels from each F-engine (each with a
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unique FID index number as shown in the table) are distributed across the 50 GPU
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XB-engines (each with a unique XID index). The processing load for some
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XB-engine processing modes, such as HI observations using a "zoom" fine
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resolution spectrometer, is so high that the digital back end cannot process the
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full 305.1 MHz bandwidth. Usually the observer in these modes has no need for
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the full bandwidth, so we do reduced width subband processing. However, if
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channels are assigned to GPUs (XIDs) sequentially, filling up one XID with
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channels before moving on to the next, the system would fail in increased
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computational demand modes even with reduced bandwidth. The packet format
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handles this by "dealing out like playing cards" one channel per XID until all
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50 have one, then starting over for the next 50 channels, and so on. When
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processing bandwidth is reduced, the processing load is then still evenly
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distributed across all XIDs, rather than concentrated on a few. This keeps the
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workload uniform across XIDs when processing demands will not support full
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bandwidth operation.
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[Ethernet Packet Specifications](../uploads/7666d16ef1f7fb6c19a746e2dbf23508/Packet_Format_2.0.pdf)
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### 6.1.3 UDP Framer and 100 GbE
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The UDP framer was developed by the Electronic Systems Design Group of
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Rutherford Appleton Laboratories. This core converts AXI4-Stream data frames
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### Footnotes
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[^harris]: F. J. Harris, Multirate Signal Processing for Communication Systems.
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Upper Saddle River, NJ, USA: Prentice Hall PTR, 2004. |
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\ No newline at end of file |
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Upper Saddle River, NJ, USA: Prentice Hall PTR, 2004. |
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\ No newline at end of file |