... | ... | @@ -155,18 +155,6 @@ channels. After the corner turn, these jumbo packets are re-routed so that each |
|
|
GPU process 25 (out of 1300) frequency channels for all 138 (+6 spares) antenna
|
|
|
signal streams.
|
|
|
|
|
|
### 6.1.3 UDP Framer and 100 GbE
|
|
|
The UDP framer was developed by the Electronic Systems Design Group of
|
|
|
Rutherford Appleton Laboratories. This core converts AXI4-Stream data frames
|
|
|
from the F-engine packetizer into IEEE 802.3 Ethernet and IPv4 packets. The core
|
|
|
is very flexible, with a receive path, AXI4-Lite memory map control
|
|
|
interface, and optional PING and other IPv4 protocol functions. ALPCA will only
|
|
|
be using the UDP core to transmit packets and its ARP capabilities for
|
|
|
destination IP address look up. The outputs of the UDP core are then sent to our
|
|
|
custom wrapper IP for the integrated 100G CMAC PHY of the RFSoC. This core
|
|
|
implements CAUI-4 100G using RS-FEC (Reed-Solomon forward error correction) for
|
|
|
use on a 100GBASE-SR4 link.
|
|
|
|
|
|
The output data rate per each of the 12 RFSoC will be 81.8 Gbps. After being
|
|
|
distributed to the 25 HPCs (50 GPUs) the rate drops to 39.3 Gbps per HPC over
|
|
|
two 100 Gigabit NIC cards per each.
|
... | ... | |